Section: New Results

Logical time in Model-Driven Engineering of embedded systems

Participants : Frédéric Mallet, Julien Deantoni, Robert de Simone, Marie-Agnès Peraldi Frati, Matias Vara-Larsen, Arda Goknil.

In the context of our approach based on logical time to specify causalities and synchronizations on models, 3.2 , we developed an extension of the OMG OCL Object Constraint Language. Named ECL (Event Constraint Language) it provides such specifications of causalitity and synchronization at syntactic language level, which enabled then automatic generation of semantic logical time constraints for any model that conforms the language.

This year, we extended to a new challenge, using logical time constraints to coordinate models of several distinct languages used jointly for a large heterogeneous system description. This work is reported in [25] , [52] .

It was illustrated in practice in the automotive domain by coordinating together the Timed Augmented Description Language (TADL2) and the EAST-ADL language [34] , [32] (the formalisms are rather similar, but still with clear distinctions at places) .

Finally, we proposed a pattern to assemble the (possibly concurrent) semantics of a language associating our logical time constraints (based on pure clocks) with a syntactic action language (providing behavior content). By reifying events and constraints, this specification of the semantics is amenable to its composition [25] . Such approach has been, again, recently used for a first attempt to coordinate distinct behavioral models [47] .

As part of our collaboration in the DAESD associated-team with ECNU Shone-SEI in Shanghai we studied the coupling of discrete-logical with continuous-physical time models, ending with a proposal of Hybrid MARTE statecharts [19] specified in a style much like a combinaison of MARTE state diagrams and timed automata.

In another setting we presented a new model of scenarios [21] , dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). The formalism uses the logical time modeling aproach, with a strong link to synchronous semantics. We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components and product line variability. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.